Verilog Primer

Course Description:

Verilog is a widely used hardware description language used in the design of complex ASICs. Xerenet's three day Verilog Primer course addresses the core issues of the language and how it is used in the ASIC and FPGA design flows. The course comprehensively covers all of the language basics as well as covering some more fundamental aspects of design flows. Courses may be public or on-site at customer premises.

Target Audience:

Engineers who are novices in Hardware Description Languages and may need to use Verilog occasionally as part of their job.

Course Prerequisites:

A knowledge of digital design is useful to fully benefit from this course. However no hardware description language experience is necessary.

Agenda:

The course format consists of lectures in the morning and labs in the afternoon. Classes begin at 9.00am and finish at 5.30pm with an hour lunch break and 15 minutes coffee breaks during the morning and afternoon.

1. Basic Language Review module, declarations and assignments.; Procedures, event lists and assignments; Instantiations and Parameters; Operators; Timing;
2. Design Example Description of Design; Testbench;
3. The ASIC and FPGA Design Flows Design Entry, Code Coverage, Simulator and Waveform Viewers, Linting Tools, Floorplanning, Synthesis, Physical Synthesis, Scan Instertion, Static and Dynamic Timing Analysis, Formal Verification, Back Annotation, Structural Test, Formal Verification, Layout, Capacitance Extraction, Chip Finishing.
4. Scan Test Blocking Statements; Code Partitioning using an ALU Example;
5. Scan Chains, Full scan, fault coverage, ATPG, Fault models, additional test circuitry, BIST, JTAG
6. item Synthesis Tools Code Parsing, Inferrence Reports, Constraints, Synthesis Libraries,
7. item Blocking and Non-Blocking Assignments, and the delta cycle\\ Blocking Statements and Examples; Non-blocking Statements and Examples; Issues with Blocking and Non-Blocking Statements; Combinational Procedures and Event Lists; Timing Issues with Blocking and Non-blocking; Assignments; The Delta Cycle;
8. item Coding Styles Structural Coding, RTL Coding, Behavioural Coding, Testbench Coding and Finite State Machines Coding Guidelines; Code Partitioning
9. item Functions, Tasks And System Tasks tasks; Issues with tasks; Examples of task issues; System Tasks; function introduction and example; Issues and characteristics of functions; Static variables, hierarchical access and functions;
10. item Timing Simple Timing; Transport, Inertial and Delay Timing; Lumped Timing and Process Corners; Timing at the Library Level; SDF Annotation; The timescale directive; The \$time system tasks;

Course Materials:

Course attendees will receive a colour fully indexed and cross-referenced course manual, and a certificate of attendance.

To book a course, please contact us:

Telephone: +353-21-4928927
email: sales@xerenet.com
Web: www.xerenet.com
Post: Xerenet Limited
The Rubicon Centre
CIT Campus
Bishopstown
Cork
Ireland