Advanced Verilog

Course Description:

Verilog is a widely used hardware description language used in the design of complex ASICs. Xerenet's five day advanced Verilog course addresses the core issues of the language and how it is used in the ASIC design flow. The course comprehensively covers all of the language basics and moves to a more advanced level in order to provide an in-depth understanding for the user. Courses may be public or on-site at customer premises.

 

Target Audience:

Engineers who have used Verilog to design or test ASICs for six months or more are ideal candidates for this course.

 

Course Prerequisites:

A knowledge of digital design and six months experience using Verilog are necessary to fully benefit from this course.

 

Agenda:

The course format consists of lectures in the morning and labs in the afternoon. Classes begin at 9.00am and finish at 5.30pm with an hour lunch break and 15 minutes coffee breaks during the morning and afternoon.

  1. Language Review module, declarations and assignments.; Procedures, event lists and assignments; Instantiations and Parameters; Operators; Timing;

  2. FIFO Verification Example Description of FIFO Design; Simple Testbench; Advanced Testbench Architecture; Test Harness; The Tasks File;

  3. Blocking and Non-Blocking Assignments, and the delta cycle Blocking Statements and Examples; Non-blocking Statements and Examples; Issues with Blocking and Non-Blocking Statements; Combinational Procedures and Event Lists; Timing Issues with Blocking and Non-blocking; Assignments; The Delta Cycle;

  4. Position Dependent Code Blocking Statements; Code Partitioning using an ALU Example;

  5. Coding for Success Synthesis; Finite State Machines Coding Guidelines;

  6. Tasks And System Tasks tasks; Issues with tasks; Examples of task issues; System Tasks;

  7. Functions function introduction and example; Issues and characteristics of functions; Static variables, hierarchical access and functions;

  8. Random Numbers Why generate random numbers?; $random system task;

  9. Race Conditions Race Conditions Rules; Read-Write Race Conditions; Write-Write Race Conditions; Initialization Race Conditions;

  10. Verilog IEEE-1364-2001 Library and Configuration Files; Constant Functions; Bus Selects; Higher Dimensional Arrays; Arithmetic; Event Lists; File IO typecasting; Automatic Extensions; Declarations; Compiler Directives; generate statement and PERL script;

  11. Timing Simple Timing; Transport, Inertial and Delay Timing; Lumped Timing and Process Corners; Timing at the Library Level; SDF Annotation; The timescale directive; The $time and $timeformat system tasks;

  12. Programmable Language Interface (PLI 1.0) Compiling C Programs; What is PLI?; PLI Design Flow; Example PLI Routine; Utility Routines; Access Routines;

  13. The Humble case statement Standard Case Statement; Issues with default; full_case and parallel_case;


Course Materials:

Course attendees will receive a colour fully indexed and cross-referenced course manual, and a certificate of attendance.

To book a course, please contact us:


Telephone: +353-21-4209066
email: This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Web: www.xerenet.com
Post: Xerenet Limited 
The Rubicon Centre,
CIT Campus,
Bishopstown,
Cork, Ireland

 
 
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